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fedl610q485-01 issue date aug. 25, 2014 ML610Q485 8-bit microcontroller 1/25 general description this lsi is a high performance cmos 8-bit microcontroller equipped with an 8-bit cpu nx-u8/100 and integrated with peripheral functions such as synchronous serial port, uart, melody driver, and analog compartor. the cpu nx-u8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture parallel processing. additionally, it adopts th e low-/high-speed dual cloc k system, standby mode, and process that prohibits leak current at high temperatures, and is most suitable for battery-driven applications. mtp version can rewrite programs on-board, which can contribute to reduction in product development tat. the flash memory incorporated into this mtp version implements the mask rom-equivalent low-voltage operation (1.25v or higher) and low-power consumption (typically 5ua at low-speed operation), enabling volume production by the mtp version. for industrial use, ML610Q485p with the extended operating ambi ent temperature ranging from -4 0c to 85c are available. features ? cpu - 8-bit risc cpu (cpu name: nx-u8/100) - instruction system: 16-bit length instruction - instruction set: transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on - on-chip debug function - minimum instruction execution time 30.5 s (@ 32.768 khz system clock) 2 s (@ 500 khz system clock) 0.25 s (@ 4 mhz system clock) ? internal memory - internal 32kbyte flash memory (16k x 16 bits) (including unusable 1k byte test area) - internal 2kbyte ram (2048 x 8 bits) ? interrupt controller - 1 non-maskable interrupt source: internal source: 1 (watchdog timer) - 28 maskable interrupt sources: internal source: 16 (ssio0, timer0, timer1, timer 2, timer 3, timer c, timer d, uart0, melody 0, pwm0, tbc128hz, tbc32hz, t bc16hz, tbc2hz, analog comparator, rtc) external source: 12 (p00, p01, p02, p03, p50, p51, p52, p53, p54, p55, p56, p57) (one interrupt request is generated from p50 to p57 interrupt sources.) ? time base counter - low-speed time base counter x 1 channel frequency compensation (compensation range: approx. -488ppm to +488ppm. compensation accuracy: approx. 0.48ppm) - high-speed time base counter x 1 channel ? real time clock ? year, month, day, hour, minute, and second registers ? adjustable to compensate for crystal variations ? automatic leap year correction ? regular interrupts (0.5 sec, 1 sec, 1 minute)
fedl610q485-01 ML610Q485 2/25 ? watchdog timer - non-maskable interrupt and reset - free running - overflow period: 4 types selectable (125ms, 500ms, 2s, 8s) ? timers - 8 bits x 6 channels [also available is 16-bit x 3 configuration (using timers 0-1, 2-3, or c-d) ] - clock frequency measurement function mode (16-bit configuration using timers 2 and 3 x 1 channel only) - the timer c and timer d are controlled by the external trigger. - the timer c and timer d are used for the one-shot timer mode. ? pwm - resolution 16 bits 1 channel ? capture - time base capture x 2 channels (4096 hz to 32 hz) ? synchronous serial port - master/slave selectable 1 channel - lsb first/msb first selectable - 8-bit length/16-bit length selectable ? uart - txd/rxd 1 channel - bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits - positive logic/negative logic selectable - built-in baud rate generator ? melody driver - scale: 29 types (melody sound frequency: 508 hz to 32.768 khz) - tone length: 63 types - tempo: 15 types - buzzer output mode (4 output modes, 8 frequencies, 16 duty levels) ? analog comparator - operating voltage: v dd =1.8v 3.6v - common mode input voltage: 0.2v vdd 0.2v - input offset voltage: 30mv(max) - interrupt allow edge selection and sampling selection - the rc discharged type a/d convertor is configured with the timers c and d. - the temperature measurement function using built-in temperature sensor. temperature measurement range: -20c to +70c (p version:-40c to +85c) - the reference voltage can be switched between cmpp0, cmpp1, cmpm0, cmpm1, 1/4vdd, 1/2vdd, temperature sensor and the internal 0.7v voltage source. ? general-purpose ports - input-only port: 4 channels (including secondary functions) - output-only port: 6 channels (including secondary functions) - input/output port: 16 channels (including secondary functions)
fedl610q485-01 ML610Q485 3/25 ? random number generator - ring oscillator based entropy source ? reset - reset through the reset_n pin - power-on reset generation when powered on - reset by the watchdog timer (wdt) overflow - reset by the low-speed oscillation stop detection ? clock - low-speed clock (operation of this lsi is not guaranteed under a condition with no supply of low-speed crystal oscillation clock) crystal oscillation (32.768 khz) - high-speed clock built-in rc oscillation (500 khz, 4 mhz) ? power management - halt mode: suspends the instruction execution by cpu (peripheral circuits are in operating states) - stop mode: stops the low-speed oscilla tion and high-speed oscillation (operations of cpu and peripheral circuits are stopped.) - high-speed clock gear: the frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) - block control function: completely stops the operation of any function block circuit that is not used (resets registers and stops clock) - when lsclk is selected for system clock, the power consumption can be reduced by using halver circuit. ? shipment - chip (die) - low-speed oscillation sto p detect rese t operating temperature product availability ML610Q485- wa yes -20c to +70c yes ML610Q485p- wa yes -40c to +85c yes - 48 pin plastic tqfp - low-speed oscillation sto p detect rese t operating temperature product availability ML610Q485- tb yes -20c to +70c - ML610Q485p- tb yes -40c to +85c - xxx: rom code number (xxx of the blank product is nnn) q: mtp version p: wide range temperature version (p version) wa: chip (die) tb: tqfp ? guaranteed operation range ? operating temperature: -20c to +70c (p version: -40c to +85c) ? operating voltage: v dd = 1.25v to 3.6v (2.4v to 3.6v used halver circuit)
fedl610q485-01 ML610Q485 4/25 block diagram block diagram of ML610Q485 cpu (nx-u8/100) epsw1 ? 3 psw elr1 ? 3 ecsr1 ? 3 greg 0? 15 lr dsr/csr ea alu pc timing * secondary function or tertiary function figure 1 ML610Q485 block diagram controller program memory (flash) 32kbyte sp bus ram 2k byte interrupt controller on-ch p i ice instruction decoder controller instruction register v pp tbc int 4 int 1 wdt int 6 8bit timer 6 capture 2 gpio data-bus int 5 test0 reset_n osc xt0 xt1 lsclk* power v ddx reset & test v dd v ss p00 to p03 p20 , p21 p40 to p47 p60 to p63 uart int 1 rxd0* txd0* analog comparator cmpm0* cmpp1* int 1 p50 to p57 ch1 , ch2 v ddl v hf int 1 sck0* sin0* ssio sout0* test1_n cmpp0* cmpm1* rtc int 1 melody/ buzzer int 1 md0* pwm int 1 pwm0* rng
fedl610q485-01 ML610Q485 5/25 chip pad layout ML610Q485 chip pad layout & dimension v dd 1 v ss 2 v ddl 3 ch1 4 ch2 5 v hf 6 xt0 7 xt1 8 v ddx 9 reset_n 10 test0 11 20 p53 24 p63 23 p62 22 p61 21 p60 32 v pp 31 p21 30 p20 28 p43 27 p42 26 p41 25 p40 2.00mm 2.08mm x y reset_n 12 p54 40 p55 39 p56 38 p57 37 p44 36 p45 35 p46 34 p47 33 29 v ss 19 p52 18 p51 17 p50 16 p03 15 p02 14 p01 13 p00 chip size: 2.00mm 2.08mm pad count: 40 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 2 ML610Q485 chip pin layout & dimension
fedl610q485-01 ML610Q485 6/25 pad coordinates ML610Q485 pad coordinates table 1 ML610Q485 pad coordinates chip center: x=0,y=0 ML610Q485 ML610Q485 pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 1 v dd -193 -934 21 p60 230 934 2 v ss -113 -934 22 p61 150 934 3 v ddl -33 -934 23 p62 70 934 4 ch1 47 -934 24 p63 -10 934 5 ch2 127 -934 25 p40 -90 934 6 v hf 207 -934 26 p41 -170 934 7 xt0 287 -934 27 p42 -250 934 8 xt1 447 -934 28 p43 -330 934 9 v ddx 527 -934 29 v ss -410 934 10 reset_n 607 -934 30 p20 -490 934 11 test0 687 -934 31 p21 -570 934 12 test1_n 767 -934 32 v pp -650 934 13 p00 879 -934 33 p47 -879 934 14 p01 879 -699 34 p46 -879 699 15 p02 879 -464 35 p45 -879 464 16 p03 879 -229 36 p44 -879 229 17 p50 879 6 37 p57 -879 -6 18 p51 879 241 38 p56 -879 -241 19 p52 879 476 39 p55 -879 -476 20 p53 879 711 40 p54 -879 -711
fedl610q485-01 ML610Q485 7/25 pin list primary function secondary function or tertiary function pad no. pin name i/o function secondary/ tertiary pin name i/o function 2,29 v ss ? negative power supply pin ? ? ? ? 1 v dd ? positive power supply pin ? ? ? ? 6 v hf ? power supply pin for halver circuit (internally generated) ? ? ? ? 3 v ddl ? power supply pin for internal logic (internally generated) ? ? ? ? 9 v ddx ? power supply pin for low-speed oscillation (internally generated) ? ? ? ? 32 v pp ? power supply pin for flash rom ? ? ? ? 4 ch1 ? capacitor connection pin for halver circuit ? ? ? ? 5 ch2 ? capacitor connection pin for halver circuit ? ? ? ? 11 test0 i/o test pin ? ? ? ? 12 test1_n i test pin ? ? ? ? 10 reset_n i reset input pin ? ? ? ? 7 xt0 i low-speed clock oscillation pin ? ? ? ? 8 xt1 o low-speed clock oscillation pin ? ? ? ? 13 p00/exi0/ cap0/tprun0 i input port, external interrupt, capture 0 input timer c/timer d external trigger input ? ? ? ? 14 p01/exi1/ cap1/tprun1 i input port, external interrupt, capture 1 input timer c/timer d external trigger input ? ? ? ? 15 p02/exi2/ rxd0/tprun2 i input port, external interrupt, uart0 received data timer c/timerd external trigger input ? ? ? ? 16 p03/exi3/ tprun3 i input port, external interrupt timer c/timer d external trigger input ? ? ? ? 30 p20/led0 o output port secondary lsclk o low-speed clock output 31 p21/led1 o output port secondary outclk o high-speed clock output ? ? ? ? 25 p40 i/o input/output port tertiary sin0 i ssio0 data input ? ? ? ? 26 p41 i/o input/output port tertiary sck0 i/o ssio0 synchronous clock input/output secondary rxd0 i uart data input 27 p42 i/o input/output port tertiary sout0 o ssio0 data output secondary txd0 o uart data output 28 p43 i/o input/output port tertiary pwm0 o pwm output ? ? ? ? 36 p44/t02p0ck/ tcdrun i/o input/output port, timer 0/timer 2/pwm 0 external clock input timer c/timer d external trigger input tertiary sin0 i ssio0 data input ? ? ? ? 35 p45/t13ck/ tcdrun i/o input/output port, timer 1/timer 3 external clock input timer c/timer d external trigger input tertiary sck0 i/o ssio0 synchronous clock input/output ? ? ? ? 34 p46/tcck i/o input/output port, timer c external clock input tertiary sout0 o ssio0 data output 33 p47/tdck i/o input/output port, timer d external clock input ? ? ? ? 17 p50/exi8 i/o input/output port, external interrupt secondary md0 o melody 0 output 18 p51/exi8 i/o input/output port, external interrupt ? ? ? ? 19 p52/exi8 i/o input/output port, external interrupt ? ? ? ?
fedl610q485-01 ML610Q485 8/25 primary function secondary function or tertiary function pad no. pin name i/o function secondary/ tertiary pin name i/o function 20 p53/exi8 i/o input/output port, external interrupt ? ? ? ? 40 p54/exi8/ cmpp0 i/o input/output port, external interrupt analog comparator noninverting input0 pin ? ? ? ? 39 p55/exi8/ cmpp1 i/o input/output port, external interrupt analog comparator noninverting input1 pin ? ? ? ? 38 p56/exi8/ cmpm0 i/o input/output port, external interrupt analog comparator inverting input0 pin ? ? ? ? 37 p57/exi8/ cmpm1 i/o input/output port, external interrupt analog comparator inverting input1 pin ? ? ? ? 21 p60 o output port ? ? ? ? 22 p61 o output port ? ? ? ? 23 p62 o output port ? ? ? ? 24 p63 o output port ? ? ? ?
fedl610q485-01 ML610Q485 9/25 pin description pin name i/o description primary/ secondary/ tertiary logic system reset_n i reset input pin. when this pin is set to a ?l? level, system reset mode is set and the internal section is initialized. when this pin is set to a ?h? level subsequently, program execution starts. a pull-up resistor is internally connected. ? negative xt0 i ? ? xt1 o crystal connection pin for low-speed clock. a 32.768 khz crystal resonator is connected to this pin. capacitors c dl and c gl are connected across this pin and v ss . (see appendix c measuring circuit 1) ? ? lsclk o low-speed clock output. assigned to the secondary function of the p20 pin. secondary ? outclk o high-speed clock output pin. this pin is used as the secondary function of the p21 pin. secondary ? general-purpose input port p00 to p03 i general-purpose input port. primary positive general-purpose output port p20, p21 o general-purpose output port. this cannot be used as the gener al output port when used as the secondary function. primary positive p60 to p63 o general-purpose output port. primary positive general-purpose input/output port p40 to p47 i/o general-purpose input/output port. this cannot be used as the general input/output port when used as the secondary or tertiary function. primary positive p50 to p57 i/o general-purpose input/output port. this cannot be used as the general input/output port when used as the secondary function. primary positive
fedl610q485-01 ML610Q485 10/25 pin name i/o description primary/ secondary/ tertiary logic uart txd0 o uart data output pin. this pin is used as the secondary function of the p43 pin. secondary positive rxd0 i uart data input pin. this pin is used as the secondary function of the p42 or the primary f unction of the p02 pin. primary/ secondary positive synchronous serial (ssio) sck0 i/o synchronous serial clock input/ output pin. this pin is used as the tertiary function of the p41 or p45 pin. tertiary ? sin0 i synchronous serial data input pin. this pin is used as the tertiary function of the p40 or p44 pin. tertiary positive sout0 o synchronous serial data output pi n. this pin is used as the tertiary function of the p42 or p46 pin. tertiary positive external interrupt exi0-3 i external maskabl e interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. these pins are used as the primary functions of the p00 to p03 pins. primary positive/ negative exi8 i external maskabl e interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. assigned to the primary function of the p50 to p57 pins. primary positive/ negative capture cap0 i primary positive/ negative cap1 i capture trigger input pins. the va lue of the time base counter is captured in the register synchronously with the interrupt edge selected by software. these pins are used as the primary functions of the p00 pin(cap0) and p01 pin(cap1). primary positive/ negative timer t02p0ck i external clock input pin used for both timer 0 and timer 2. this pin is used as the primary f unction of the p44 pin. primary ? t13ck i external clock input pin used for both timer 1 and timer 3. this pin is used as the primary f unction of the p45 pin. primary ? tcck i external clock input pin used for timer c. this pin is used as the primary function of the p46 pin. primary ? tdck i external clock input pin used for timer d. this pin is used as the primary function of the p47 pin. primary ? tcdrun i external trigger input pin used for timer c or timer d. this pin is used as the primary function of the p44 pin or the p45 pin. primary ? tprun0 i external trigger input pin used for timer c or timer d. this pin is used as the primary func tion of the p00 pin. primary ? tprun1 i external trigger input pin used for timer c or timer d. this pin is used as the primary func tion of the p01 pin. primary ? tprun2 i external trigger input pin used for timer c or timer d. this pin is used as the primary func tion of the p02 pin. primary ? tprun3 i external trigger input pin used for timer c or timer d. this pin is used as the primary func tion of the p03 pin. primary ? led drive led0, led1 o n-channel open drain output pi ns to drive led. this pin is used as the primary function of the p20 and the p21 pins. primary positive /negative
fedl610q485-01 ML610Q485 11/25 pin name i/o description primary/ secondary/ tertiary logic melody md0 o melody/buzzer signal output pin. this pin is used as the secondary function of the p50 pin. secondary positive/ negative pwm pwm0 o pwm0 output pin. this pin is used as the tertiary function of the p43 pin. tertiary positive t02p0ck i pwm0 external clock input pin. this pin is used as the primary function of the p44 pin. primary ? analog comparator cmpp0 i analog comparator noninverting in put0 pin. this pin is used as the primary function of the p54. primary ? cmpp1 i analog comparator noninverting in put1 pin. this pin is used as the primary function of the p55. primary ? cmpm0 i analog comparator inverting i nput0 pin. this pin is used as the primary function of the p56. primary ? cmpm1 i analog comparator inverting i nput1 pin. this pin is used as the primary function of the p57. primary ? test test0 i/o pin for testing. a pull-down resistor is internally connected. ? positive test1_n i pin for testing. a pull-up resistor is internally connected. ? negative power supply v ss ? negative power supply pin. ? ? v dd ? positive power supply pin. ? ? v hf ? positive power supply pin (internally generated) for halver. capacitor c hf (see measuring circuit 1) should be connected between this pin and v ss . ? ? v ddl ? positive power supply pin (internally generated) for internal logic. capacitors c l (see measuring circuit 1) are connected between this pin and v ss . ? ? v ddx ? positive power supply pin (internally generated) for low-speed oscillation. capacitor c x (see measuring circuit 1) should be connected between this pin and v ss . ? ? ch1 ? ? ? ch2 ? capacitor connection pin for halver circuit. capacitor c h12 (see measuring circuit 1) are connected between ch1 and ch2. ? ? v pp ? power supply pin for programming flash rom. a pull-down resistor is internally connected. ? ?
fedl610q485-01 ML610Q485 12/25 termination of unused pins table 2 shows methods of terminating the unused pins. table 2 termination of unused pins pin recommended pin handling v pp open reset_n open test0 open test1_n open p00 to p03 v dd or v ss p20, p21 open p40 to p47 open p50 to p57 open p60 to p63 open note: it is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting.
fedl610q485-01 ML610Q485 13/25 electrical characteristics absolute maximum ratings (v ss = 0v) parameter symbol condition rating unit power supply voltage 1 v dd ta=25c -0.3 to +4.6 v power supply voltage 2 v pp ta=25c -0.3 to +9.5 v power supply voltage 3 v ddl ta=25c -0.3 to +3.6 v input voltage v in ta=25c -0.3 to v dd +0.3 v output voltage v out ta=25c -0.3 to v dd +0.3 v output current 1 i out1 port 4 to 6, ta=25c -12 to +11 ma output current 2 i out2 port 2, ta=25c -12 to +20 ma power dissipation pd ta=25c 0.9 w storage temperature t stg D -55 to +150 c recommended operating conditions (v ss = 0v) parameter symbol condition range unit without p version -20 to +70 operating temperature t op p version -40 to +85 c f op =30k to 625khz 1.25 to 3.6 f op =30k to 5mhz 1.8 to 3.6 operating voltage v dd f op =30k to 36khz, used halver 2.4 to 3.6 v v dd =1.25 to 3.6v 30k to 625k v dd =1.8 to 3.6v 30k to 5.0m operating frequency (cpu) f op v dd =2.4 to 3.6v, used halver 30k to 36k hz low-speed crystal oscillation frequency f xtl D 32.768k hz c dl D 3 to 18 low-speed crystal oscillation external capacitance c gl D 3 to 18 pf v ddl pin external capacitance c l D 2.230% f v ddx pin external capacitance c x D 0.130% f v hf pin external capacitance c hf D 0.130% f pin-to-pin (ch1 to ch2) external capacitance c h12 D 0.130% f
fedl610q485-01 ML610Q485 14/25 operating conditions of flashrom (vss= 0v) parameter symbol condition range unit operating temperature t op at write/erase 0 to +40 c v dd at write/erase 2.75 to 3.6 v ddl at write/erase *1 2.5 to 2.75 operating voltage v pp at write/erase 7.7 to 8.3 v rewrite count c ep D 80 cycles data retention y dr D 10 years *1 : when writing to and erasing on the flash memory, the vo ltage in the specified range needs to be supplied to the v ddl pin. the v pp pin has an internal pull-down resistor. operation conditions of comparator (v dd =1.8 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c fo r p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measurement circuit common-mode input voltage cmv in D 0.2 D v dd -0.2 v analog comparator input offset voltage v cmpof ta=25 c -30 D 30 mv analog comparator response time t cmp ta=25 c, overdrive=100mv D D 1 s analog comparator wakeup time t cmpw D D D 5 s analog comparator supply current i cmp ta=25 c D 33 45 a temperature sensor output voltage through x2 v tmp ta=25 c D 1355 D mv ta = -40 to +25c D -3.585 D temperature sensor output voltage through x2 (temperature property) v tmp ta = 25 to 85c D -3.718 D mv/c 0.7v voltage source output voltage through x2 v ref ta=25 c 1.386 1.400 1.414 v 0.7v voltage source temperature deviation v ref D D 0 D %/c 0.7v voltage source supply current i ref ta=25 c D 20 40 a 1/2 vdd voltage source vdd2 D vdd/2 x 0.96 vdd/2 vdd/2 x 1.04 v 1/4 vdd voltage source vdd4 D vdd/4 x 0.96 vdd/4 vdd/4 x 1.04 v 1
fedl610q485-01 ML610Q485 15/25 dc characteristics (1/4) (vdd=1.25 to 3.6v, vss=0v, ta=-20 to +70c, ta=-40 to +85c for p version, unl ess otherwise specified) rating parameter symbol condition min. typ. max. unit measure ment circuit ta=25c typ. -10% 500 typ. +10% khz v dd =1.25 to 3.6v * 2 typ. -25% 500 typ. +25% khz ta=25 c typ. -10% 4.0 typ. +10% mhz 500khz/4mhz rc oscillation frequency f rc v dd =1.8 to 3.6v * 2 typ. -25% 4.0 typ. +25 % mhz low-speed crystal oscillation start time* 1 t xtl D D 0.6 2 s 500khz/4mhz rc oscillation start time t rc D D D 3 s reset pulse width p rst D 200 D D reset noise elimination pulse width p nrst D D D 0.3 s power-on reset generated power rise time t por D D D 10 ms 1 * 1 : 32.768khz crystal resonator dt-26 (load capacitanc e 6pf) (made by kds:daishinku corp.) is used (c gl =c dl =6pf). * 2 : recommended operating temperature (ta=-20 to 70c, ta=-40 to 85c for p version) reset_n external reset sequence vdd 0.9xv dd 0.1xv dd t por power on reset sequence p rst vil1 vil1
fedl610q485-01 ML610Q485 16/25 dc characteristics (2/4) (v dd =3.0v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit ta=25 c D 0.32 0.8 supply current 1 idd1 cpu: in stop state. low-speed/high-speed oscillation: stopped. * 4 D D 8 a ta=25 c D 0.35 0.7 supply current 2 idd2 cpu: in halt state. (ltbc, wdt: operating)* 2 * 3 . high-speed 500khz/4mhz oscillation: stopped. used halver * 4 D D 4 a ta=25 c D 4.5 8 supply current 3-1 idd3-1 cpu: in 32.768khz operating state.* 1 * 2 high-speed 500khz/4mhz oscillation: stopped, not used halver * 4 D D 15 a ta=25 c D 2.5 4 supply current 3-2 idd3-2 cpu: in 32.768khz operating state.* 1 * 2 high-speed 500khz/4mhz oscillation: stopped, used halver * 4 D D 7.5 a ta=25 c D 75 100 supply current 4-1 idd4-1 cpu: in 500khz rc operating state. not used halver * 4 D D 120 a ta=25 c D 600 750 supply current 4-2 idd4-2 cpu: in 4mhz rc operating state. not used halver * 4 D D 800 a 1 * 1 : when the cpu operating rate is 100% (no halt state). * 2 : 32.768khz crystal resonator dt-26 (load capacitanc e 6pf) (made by kds:daishinku corp.) is used (c gl =c dl =6pf) * 3 : significant bits of blkcon0 to blkcon3 registers are all ? 1?. * 4 : recommended operating temperature (ta=-20 to 70 c, ta=-40 to 85 c for p version)
fedl610q485-01 ML610Q485 17/25 dc characteristics (3/4) (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c fo r p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit ioh1=-0.5ma, v dd =1.8 to 3.6v v dd -0.5 D D voh1 ioh1=-0.03ma, v dd =1.25 to 3.6v v dd -0.3 D D iol1=+0.5ma, v dd =1.8 to 3.6v D D 0.5 output voltage 1 (p20, p21 (n-channel open drain output mode is not selected)) (p40 to p47) (p50 to p57) (p60 to p63) vol1 iol1=+0.1ma, v dd =1.25 to 3.6v D D 0.3 output voltage 2 (p20, p21 (n-channel open drain output mode is selected)) vol2 iol2=+5ma, v dd =1.8 to 3.6v D D 0.5 v 2 iooh voh=v dd (in high-impedance state) D D 1 output leakage (p20, p21) (p40 to p47) (p50 to p57) (p60 to p63) iool vol=v ss (in high-impedance state) -1 D D a 3 iih1 vih1=v dd D D 1 input current 1 (reset_n, test1_n) iil1 vil1=v ss -600 -300 -2 iih2 vih2=v dd 2 300 600 input current 2 (test0) iil2 vil2=v ss -1 D D vih3=v dd, v dd =1.8 to 3.6v (when pulled-down) 2 30 200 iih3 vih3=v dd, v dd =1.25 to 3.6v (when pulled-down) 0.01 30 200 vil3=v ss, v dd =1.8 to 3.6v (when pulled-up) -200 -30 -2 iil3 vil3=v ss, v dd =1.25 to 3.6v (when pulled-up) -200 -30 -0.01 iih3z vih3=v dd (in high-impedance state) D D 1 input current 3 (p00 to p03) (p40 to p47) (p50 to p57) iil3z vil3=v ss (in high-impedance state) -1 D D a 4
fedl610q485-01 ML610Q485 18/25 dc characteristics (4/4) (vdd=1.25 to 3.6v, vss=0v, ta=-20 to +70c, ta=-40 to +85c for p version, unle ss otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit vih1 D 0.7 v dd D v dd input voltage 1 (reset_n) (test1_n) (test0) (p00 to p03) (p40 to p47) (p50 to p57) vil1 v dd =1.25 to 3.6v 0 D 0.2 v dd v 5 input pin capacitance (p00 to p03) (p40 to p47) (p50 to p57) cin f=10khz v rms =50mv ta=25c D D 5 pf D
fedl610q485-01 ML610Q485 19/25 measuring circuits measuring circuit 1 xt0 xt1 a v dd v ddl c l v ss c v : 2.2 f c l : 2.2uf cx : 0.1 f c hf : 0.1 f c h12 : 0.1 f 32.768khz crystal resonator : dt-26 (load capacitance 6pf) (made by kds:daishinku corp.) c gl , c dl : 6pf c v v ddx c x c h12 ch2 ch1 32.768khz crystal resonator c gl c dl v hf c hf measuring circuit 2 input pin v v dd v ddl v ss vih vil output pin (note 1): input logic circuit to determi ne the specified measuring conditions. (note 2) repeats for t he specified output pin (note 2) (note 1) v ddx
fedl610q485-01 ML610Q485 20/25 measuring circuit 3 input pin a v dd v ddl v ss vih vil output pin (note 1): input logic circuit to determi ne the specified measuring conditions. (note 2) repeats for t he specified output pin (note 2) (note 1) v ddx measuring circuit 4 input pin a v dd v ddl v ss output pin (note 3) repeats for t he specified input pin (note 3) v ddx
fedl610q485-01 ML610Q485 21/25 measuring circuit 5 input pin v dd v ddl v ss vih vil output pin (note 1): input logic circuit to determi ne the specified measuring conditions. (note 1) waveform observation v ddx
fedl610q485-01 ML610Q485 22/25 ac characteristics (external interrupt) (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c fo r p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit external interrupt disable period t nul interrupt: enabled (mie = 1), cpu: nop operation system clock: 32.768khz 76.8 D 106.8 s t nul p00 to p03 (rising-edge interrupt) p00 to p03 (falling-edge interrupt) p00?p03 (both-edge interrupt) t nul t nul ac characteristics (uart) (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c fo r p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit transmit baud rate t tbrt D D brt* 1 D s receive baud rate t rbrt D brt* 1 -3% brt* 1 brt* 1 +3% s * 1 : baud rate period (including the error of the clock frequency sele cted) set with the uart baud rate register (ua0brtl,h) and the uart mode register 0 (ua0mod0). t rbrt txd0* rxd0* *: indicates the secondary function of the port. t tbrt
fedl610q485-01 ML610Q485 23/25 ac characteristics (synchronous serial port) (v dd = 1.25 to 3.6v, v ss = 0v, ta = ? 20 to +70 c, ta = ? 40 to +85 c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit when rc oscillation is 500khz * 2 (v dd = 1.25 to 3.6v) 10 ? ? sclk0 input cycle (slave mode) t scyc when rc oscillation is 4mhz * 3 (v dd = 1.8 to 3.6v) 2 ? ? s sclk0 output cycle (master mode) t scyc ? ? sclk0* 1 ? s when rc oscillation is 500khz * 2 (v dd = 1.25 to 3.6v) 4 ? ? sclk0 input pulse width (slave mode) t sw when rc oscillation is 4mhz * 3 (v dd = 1.8 to 3.6v) 04 ? ? s sclk0 output pulse width (master mode) t sw ? sclk0* 1 0.4 sclk0* 1 0.5 sclk0* 1 0.6 s when rc oscillation is 500khz * 2 (v dd = 1.25 to 3.6v) output load 10pf ? ? 500 sout0 output delay time (slave mode) t sd when rc oscillation is 4mhz * 3 (v dd = 1.8 to 3.6v) output load 10pf ? ? 240 ns when rc oscillation is 500khz * 2 (v dd = 1.25 to 3.6v) output load 10pf ? ? 500 sout0 output delay time (master mode) t sd when rc oscillation is 4mhz * 3 (v dd = 1.8 to 3.6v) output load 10pf ? ? 240 ns sin0 input setup time (slave mode) t ss ? 80 ? ? ns when rc oscillation is 500khz * 2 (v dd = 1.25 to 3.6v) 500 ? ? sin0 input setup time (master mode) t ss when rc oscillation is 4mhz * 3 (v dd = 1.8 to 3.6v) 240 ? ? ns when rc oscillation is 500khz * 2 (v dd = 1.25 to 3.6v) 300 ? ? sin0 input hold time t sh when rc oscillation is 4mhz * 3 (v dd = 1.8 to 3.6v) 80 ? ? ns *1: clock period selected with s0ck3?0 of the serial port n mode register (sio0mod1) * 2 : when 500khz rc oscillation is selected by oscm 3 of the frequency cont rol register (fcon0) * 3 : when 4mhz rc oscillation is selected by os cm3 of the frequency control register (fcon0) t sd sclk0* sin0* sout0* *: indicates the secondary function of the port t sd t ss t sh t sw t sw t scyc
fedl610q485-01 ML610Q485 24/25 revision history page document no. date description previous edition current edition fedl610q485-01 aug.25,2014 ? ? final edition 1
fedl610q485-01 ML610Q485 25/25 notes no copying or reproduction of th is document, in part or in whole, is permitte d without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage an d operations of the products. the peripheral conditions must be ta ken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or mispri nt of such information, lapis semiconduc tor shall bear no re sponsibility for such damage. the technical information specified herein is intended only to show the typical functions of an d examples of application circui ts for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and ot her parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of su ch technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the fa ilure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsib ility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of h uman injury (such as a medical instrument, tran sportation equipment, aerospace machinery, nuclear-reactor contro ller, fuel-controlle r or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2014 lapis semiconductor co., ltd. 2-4-8 shinyokohama, kouhoku-ku, yokohama 222-8575, japan http://www.lapis-semi.com/en/

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